Efficient scheduling mapping algorithm for row parallel coarse-grained reconfigurable architecture

Row Parallel Coarse-Grained Reconfigurable Architecture (RPCGRA) has the advantages of maximum parallelism and programmable flexibility. Designing an efficient algorithm to map diverse applications onto RPCGRA is difficult due a number hardware constraints. To solve this problem, nodes data flow graph must be partitioned scheduled RPCGRA. In paper, we present Depth-First Greedy Mapping (DFGM) that simultaneously considers communication costs use times Cell Array (RCA). Compared with level breadth mapping, performance DFGM better. The percentage improvement in RCA 33% non-original input output 64.4% (Given Discrete Cosine Transfor 8 (DCT8), area reconfigurable processing unit 56). level-based depth also obtains lowest averages RCA, times, time.